The invention relates to a device for processing a data stream, the device comprising a clock recovery system for locking a clock frequency to a time base of the data stream by comparing the clock frequency to time stamps representing the time base.
The invention further relates to a method of locking a clock frequency to a time base of a data stream by comparing the clock frequency to time stamps representing the time base.
U.S. Pat. No. 5,699,392 discloses a system for the recovery of an encoder clock from an MPEG-2 transport stream. The frequency of a decoder clock is maintained at approximately the same frequency as an encoder clock, based on program clock reference (PCR) values contained in a digital information stream. A voltage-controlled oscillator produces a decoder clock frequency of 27 MHz. The decoder clock is fed back to a counter to produce a local system time clock (STC). The counter is initially loaded with a PCR value from the digital data stream. As subsequent PCR values are received, a subtractor subtracts the value of the PCR from the value of the local STC to produce an error signal. To produce a control signal, the error signal is filtered, scaled, and added to a control variable within a low-pass filter and processor. The control signal is applied to the voltage-controlled oscillator to adjust the oscillation frequency of the oscillator.
The MPEG standards provide for the transmission of digital information from multiple sources by dividing the digital data into a number of packets. The packets are then multiplexed onto a single data channel, allowing a relatively large number of users to transmit and receive data over a common data channel. All audio, video and auxiliary information to be carried within a given data channel is divided into 188-byte long transport packets. Each transport packet is subdivided into a header and a payload. The header carries information to identify the type of data that is carried within the payload and information required for decoding the transport packet stream. The PCR is a 42-bit value that represents time stamps from a relative STC that is clocked by an encoder clock within an MPEG-2 encoder. Of the 42 bits, the first 33 bits of the PCR value are referred to as the PCR base, and express a value of the encoder system time clock in 90 kHz time base units. The remaining 9 bits of the PCR value are referred to as the PCR extension, and express a value of the system time clock in 27 MHz (modulo 300) time base units. The MPEG-2 standard requires that the PCR values must be provided at intervals of no more than 100 ms in the transport stream. The PCR values within the MPEG-2 transport stream are used to accurately recover the encoder clock in the MPEG-2 decoder. It is necessary to maintain accurate synchronization between the encoder clock used to encode the data and the decoder clock used to decode the data in order to properly demultiplex and decode the audio and video data. A difference in the encoder and decoder clock frequencies causes buffer underflow or overflow.
The transport stream is provided with presentation time-stamps (PTS) to indicate to the MPEG-2 decoder when to present the individual frames of video and audio data to the user. The value of each PTS is ultimately dictated by the frequency of the encoder clock in the encoder, which clocks an STC in the MPEG-2 encoder. When encoding the data, the MPEG-2 encoder inserts the PTS into the transport stream based on samples of the STC. The decoder clock in the MPEG-2 decoder must therefore operate at the same frequency as the encoder clock if the data streams are to be properly presented to a user. For purposes of this description,xe2x80x9csynchronizationxe2x80x9d between the encoder clock and the decoder clock implies that the clocks are operating at the same frequency, but with a possible phase offset between them.
Assuming an error-free environment, synchronizing the encoder and the decoder clocks eliminates frame skips or frame holds that occur when displaying the transmitted data. A frame skip can occur when data is received later than its PTS denotes. A frame hold can occur when the buffer within the decoder receives insufficient audio or video data to perform the decoding. To maintain synchronization, a phase locked loop is provided in the clock recovery system. The voltage-controlled oscillator operates at a nominal oscillation frequency of 27 MHz and has a control input to adjust the frequency within a small range surrounding the 27 MHz nominal frequency. The decoder clock is used for demultiplexing, decoding and displaying the audio and video.
An object of the invention is, inter alia, to provide a more flexible and cost-effective clock recovery system. To this end, the invention provides a data processing device and a method of locking a clock frequency to a time base of a data stream as defined in the independent claims. Advantageous embodiments are defined in the dependent claims.
A first embodiment of the invention is characterized in that said clock recovery system comprises: a free running clock for generating a free running reference frequency; and means for synthesizing said clock frequency from said reference frequency under control of said time stamps. A free running clock is more cost-effective than a de-tunable crystal as is used in embodiments that are known from the prior art. Faster locking and a larger tracking range can be achieved. The invention further offers more flexibility in choosing another frequency.
An embodiment of the invention comprises further means for synthesizing a further clock frequency from said reference frequency without locking to said time base. A further clock frequency for which locking to the time base of the incoming data stream is not necessary, is generated from the free running reference frequency, for example by a dedicated phase locked loop. This embodiment provides a clock system that provides locked clocks as well as unlocked clocks. The free running reference frequency is used for both types of clocks as a reference clock. Locking is only performed for those clocks that really need locking, e.g. clocks for use in MPEG audio and video processing units. In a practical embodiment of the invention, said further means comprise a multiplier for multiplying said reference frequency by an appropriate integer number to obtain said further clock frequency. If such a multiplier is implemented by use of a phase locked loop, integer dividers are required, thus simplifying the design. Clock skew, due to different load of the individual clock trees, between various blocks is minimized and data can be exchanged without additional synchronization circuitry.
In a further embodiment of the invention, said synthesizing means comprise a controlled multiplier for multiplying the reference frequency by an appropriate number to obtain said clock frequency, said appropriate number being derived under control of said time stamps. For flexibility, the appropriate number is made controllable by a processing unit. Locking to the time base of the incoming data stream is achieved by comparing the locked clock frequency with the incoming time stamps and to calculate the appropriate number by the processing unit.
In a practical embodiment, the controlled multiplier comprises a phase locked loop (PLL) circuit for obtaining an oscillation frequency at an integer multiple of the reference frequency, said circuit comprising a phase detector coupled to an oscillator, and a feedback loop for feeding the oscillation frequency to an input of the phase detector, said feedback loop comprising an integer divider; and a controlled divider for dividing the oscillation frequency by a non-integer divider number to obtain a divided frequency, said divider number being derived under control of said time stamps and said divided frequency being output as the clock frequency. This is a practical implementation of the invention, in which the feedback loop only needs a simple integer divider. Since this straight forward implementation of the synthesizing means for locking the clock frequency by the use of a phase locked loop does not minimize clock jitter and clock skew, some special measures are defined in further embodiments.
In a clock skew reducing embodiment of the invention, said controlled multiplier comprises: a phase locked loop circuit for obtaining an oscillation frequency at an integer multiple of the reference frequency, said circuit comprising a phase detector coupled to an oscillator; a controlled divider for dividing the oscillation frequency by a non-integer divider number to obtain a divided frequency, said divider number being derived under control of said time stamps; a counter for counting the number of positive edges in the divided frequency per cycle of the reference frequency; means for generating a predetermined frequency comprising an amount of positive edges at predetermined positions, said amount being equal to said number of positive edges in the divided frequency and said predetermined frequency being output as the clock frequency; and a feedback loop for feeding the clock frequency to an input of the phase detector, said feedback loop comprising an cascaded divider being arranged to divide the clock frequency by a divider number equal to said number of positive edges.
An advantageous embodiment of the invention comprises means for synthesizing clock frequencies for audio processing and video processing independently. Locking the audio and video clocks independently has the additional advantage that even PTS time stamps can be involved in the regulation by which an exact time base match can be achieved. Also time base discontinuities can be optimized independently.
A further embodiment comprises first processing means for performing a first processing step with use of said clock frequency; second processing means for performing a second processing step with use of said further clock frequency; and a sample rate converter for converting a sample rate of an output signal of the first processing means to furnish converted output signals to the second processing means. This embodiment provides a solution for coupling a unit that runs on a locked clock frequency and a second unit that runs on an unlocked, i.e. a different frequency. The sample rate converters compensate for the clock jitter, so that no difficult high performance analog PLL""s are required. This embodiment is especially useful for running audio and video processing units on a locked clock frequency and digital to analog converters coupled to the processing units on an unlocked clock frequency. In an advantageous embodiment, the D/A converter for the video part runs at an integer multiple of the clock frequency of the audio D/A converter. This integer can be equal to one, so that the audio and video D/A converters run at the same clock frequency. The same clock frequency or a simple mutual clock ratio for audio and video D/A converters simplifies the integration on the same chip. The sample rate converter may be controlled by phase information out of the controlled multiplier.
The aforementioned and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.